新闻中心

EEPW首页 > 嵌入式系统 > 业界动态 > Andes Announces Advanced SoC Development Environments for V5 AndesCore™ N25 and NX25 Processors with Tool Partners

Andes Announces Advanced SoC Development Environments for V5 AndesCore™ N25 and NX25 Processors with Tool Partners

作者:时间:2017-11-29来源:电子产品世界

HsinChu, Taiwan, November 20,2017 - Andes Technology Corporation(TWSE:6533), the leading Asia-based supplier of compact, low-power,high-performance 32/64-bit embedded CPU cores and a founding member of RISC-VFoundation, today announces the partnership with the world-class tools vendors includingImperas, Lauterbach, Mentor, a Siemens Business, and Ultra (in alphabeticalorder) to bring their system-on-chip () development environments to Andes V5processors and the RISC-V community.

本文引用地址:http://www.eepw.com.cn/article/201711/372224.htm


Andes is a 12-year-old CPU IP vendor with solutions serving in excess of2-Billion s covering a wide range of applications. As a natural evolution,Andes has adoped RISC-V as the subset of its fifth generation architecture, theAndeStar™ V5, and brings it to the RISC-V community. Based on the V5 architecture,Andes announced two high-performance 1+GHz AndesCore™ processor IP’s, the 32-bit N25 andthe 64-bit NX25, both delivering over 2.8 DMIPS/MHz and over 3.4 CoreMark/MHz, and gate count assmall as 30K and 50K, respectively, when using TSMC 28nm HPC process. The N25 and NX25 are ideal for high-speedcontrol tasks in networking, storage, and AI applications.


To support the ever-increasing features of the emergingapplications, SoC engineers face the challenges of the design complexity andtime-to-market. They need powerful development tools such as fast systemsimulation for architectural exploration and SW development, emulation forfunctional verification and system validation, performance optimization, toughbugs tracing and embedded analytics. That is why Andes has worked with some ofthe partners on V3 AndesCore™ processors for many years,” Frankwell Jyh-MingLin, President of Andes Technology, commented, “We are now collaborating withImperas, Lauterbach, Mentor, and UltraSoC to provide those advanced developmenttools for our new V5 AndesCore™ N25 and NX25, and the RISC-V community. We areexcited to enrich the ecosystem of RISC-V with our partners’ great support, andlook forward to the creative products from our common customers in the nearfuture.”


"Imperassupports Andes with Open Virtual Platforms (OVP) Fast Processor Models of theAndeStar™ V5 processors and with virtual platform- based tools to help with thedevelopment, porting, debug and test of software and operating systems runningon the V5 processors. Building on our partnership with Andes, Imperas ispleased to deliver our next-generation models, Extendable Platform Kits (EPKs)and software development solutions for the emergent RISC-V ecosystem, to helpaccelerate their adoption." said Simon Davidmann, CEO of Imperas.


Norbert Weiss, international sales and marketing managerand head of marketing at Lauterbachcommented: “For many years, Lauterbach TRACE32 has supported AndeStar™ V3architecture and cores. We are happy to continuously support the new V5processors, N25 and NX25, RISC-V based with enhanced extension architecture.With TRACE32, the developers who are creating products around Andes new V5processors have access to a full range of debug functionality, from bootstrapcode to interrupt routines and drivers. ”


Mentor’s work with Andes means that mutual customers are assuredthat the best emulation platform support is available for the Andes’ N25 andNX25 processor IP’s,” said Eric Selosse, vice president and general manager ofthe Mentor Emulation Division. “Our support for the V5 AndesCore processors, onthe Veloce® emulation platform, helps streamline and simplify the design andcreation of SoCs based on the N25 and NX25.”


UltraSoC is committed to increasing the number of silicon designstarts, and our participation in Andes V5 processors,” said Rupert Baines, CEOof UltraSoC, “We are committed to supporting the adoption of RISC-V throughoutthe semiconductor industry, both through our membership in the RISC-VFoundation and via individual partnerships. Making UltraSoC’s on-chip trace anddebug IP available through Andes V5 processors will enable chipmakerseverywhere to leverage the benefits of open source hardware and introduces newinnovative designs to the market.”


Andes, the first mainstream CPU IP vendor to adopt RISC-Vinstruction set architecture, has been actively contributing for GNU and LLVMtoolchains since it joined the RISC-V Foundation. The V5 NX25 and N25processors are fast and small 5-pipeline CPU IPs with abundant extensionfeatures based on feedback from customer interactions over the past 12 years. Andesis committed to driving the acceleration of the acceptance of the RISC-V withour partners.

About Imperas

Imperas provides methodologies, technologiesand products to enable the efficient development, debug and test of softwarefor embedded systems. Imperas users come from the processor IP market,semiconductor vendors, and embedded systems companies with strong requirementsfor software quality and reliability, as well as functional safety andsecurity. Imperas virtual platform based products use Open Virtual Platforms(OVP) models and APIs, supporting over 180 different processor cores, includingRISC-V cores. For more informationabout Imperas, please see www.imperas.com. Follow Imperason twitter @ImperasSoftware, on LinkedIn andvisit YouTube.




关键词: SoC

评论

技术专区

关闭