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RK3568 is a high-performance and low power quad-core application processor designed for personal mobile internet device and AIoT equipments.
Many embedded powerful hardware engines are provided to optimize performance for high- end application. RK3568 supports almost full-format H.264 decoder by 4K@60fps, H.265 decoder by 4K@60fps, also support H.264/H.265 encoder by 1080p@60fps, high-quality JPEG encoder/decoder.
Embedded 3D GPU makes RK3568 completely compatible with OpenGL ES 1.1/2.0/3.2, OpenCL 2.0 and Vulkan 1.1. Special 2D hardware engine will maximize display performance and provide very smoothly operation.
The build-in NPU supports INT8/INT16/FP16/BFP16 hybrid operation. In addition, with its strong compatibility, network models based on a series of frameworks such as TensorFlow/MXNet/PyTorch/Caffe can be easily converted.
RK3568 has high-performance external memory interface(DDR3/DDR3L/DDR4
/LPDDR3/LPDDR4/LPDDR4X) capable of sustaining demanding memory bandwidths.
1.2 FeaturesThe features listed below which may or may not be present in actual product, may be subject to the third party licensing requirements. Please contact Rockchip for actual product feature configurations and licensing requirements.
1.2.1 Microprocessor
l Quad-core ARM Cortex-A55 CPU
l
ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
l Include VFP hardware to support single and double-precision operations
l ARMv8 Cryptography Extensions
l Integrated 32KB L1 instruction cache, 32KB L1 data cache with ECC
l 512KB unified system L3 cache with ECC
l TrustZone technology support
l Separate power domains for CPU core system to support internal power switch and externally turn on/off based on different application scenario
n PD_A55_0: 1st Cortex-A55 + Neon + FPU + L1 I/D Cache
n PD_A55_1: 2nd Cortex-A55 + Neon + FPU + L1 I/D Cache
n PD_A55_2: 3rd Cortex-A55 + Neon + FPU + L1 I/D Cache
n PD_A55_3: 4th Cortex-A55 + Neon + FPU + L1 I/D Cache
l One isolated voltage domain
1.2.2 Neural Process Unit
l Neural network acceleration engine with processing performance up to 1 TOPS
l Support INT8/INT16/FP16/BFP16 MAC hybrid operation
l Support deep-learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet
l One isolated voltage domain
1.2.3 Memory Organization
l Internal on-chip memory
n BootROM
n SYSTEM_SRAM in the voltage domain of VD_LOGIC
n PMU_SRAM in the voltage domain of VD_PMU for low power application
l External off-chip memory
n DDR3/DDR3L/DDR4/LPDDR3/LPDDR4/LPDDR4X①
n SPI Nor/Nand Flash
n eMMC
n SD_Card
n 8bits Async Nand Flash
n 8bits toggle Nand Flash
n 8bits ONFI Nand Flash
1.2.4
Internal Memoryl Internal BootRom
n Support system boot from the following device:
u SPI Flash interface
u Nand Flash
u eMMC interface
u SDMMC interface
n Support system code download by the following interface:
u USB OTG interface (Device mode)
l SYSTEM_SRAM
n Size: 64KB
l PMU_SRAM
Size: 8KB
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