"); //-->
对于使用 OrCAD-Allegro 工具链进行设计的工程师来说,遵守这些准则可减少设计反复次数,提高设计质量,并避免出现软件错误的发生。益处多多!
Best practices for Capture-Allegro
Best practices for preparing a library for Capture-Allegro PCB Editor
flow
Limit part and pin names to 31 characters
Use upper case characters for part/symbol names, part references
designators, and pin names
Do not use special characters to assign part names, references
designators, and pin names
Do not use duplicate pin names for pins other than power pins
For multiple power pins with the same pin names, do not make some
pins visible and other invisible
Do not use "0" as a pin number
Best practices for Capture design for Allegro PCB Editor
While defining a net list alias or a net name
Keep the maximum length of a net name or alias up to 31
characters
Do not use lower case or special characters in a net name
Avoid using "Power Pins Visible" property at design level
Use net to connect pins
Leave room for assigning a net name. Pin-to-pin connection
changes the net name when a user moves a component
Run the Capture DRC command before generating Allegro PCB Editor
netlist
Set for Allegro PCB Editor footprint before running Netrev
Best practices for smooth back annotation
Do not change design name, hierarchical block names, or reference
designators in Capture after board files creation
Do not edit a part from schematic in Capture after board file
creation
Do not replace cache as it changes the Source library name and part
name, in capture
Do not change the values of component definition properties in
capture after board files creation
Do not change Design file/root schematic/hierarchical block names
in Capture after board file creation
Do not add or delete components to or from the schematic design
immediately after the board file creation. Add or delete components
after finishing the back annotation process
- 2 -
Do not add any additional components in Allegro PCB Editor. Instead,
add components in Capture and take them to Allegro PCB Editor
Do not add, rename, or delete a net in Allegro PCB Editor
Do not change the format for reference designators for parts in
Allegro PCB Editor as or
>-
Run Allegro PCB Editor Dbdoctor before running Back annotation by
selecting the Database Check command from the Tools menu in Allegro
PCB Editor
Make backups of the original design before updating the design with
the swap information in Capture
Back annotate the design immediately after making the board file.
Though it does not a mandatory step, back annotating the design
before placing components helps avoid problems in back-annotation
at a later stage.
If back annotation at this stage generates an empty swap file, you
can proceed with placing and routing the board file. In case any
problems are detected, you must correct them in the design file and
generate the board file again until an empty swap file is generated.
专栏文章内容及配图由作者撰写发布,仅供工程师学习之用,如有侵权或者其他违规问题,请联系本站处理。 联系我们
相关推荐
\"养龙虾\"竟变引狼入室? 揭秘358亿美元商机背后疯狂真相
赛灵思Virtex-7 GTX收发器演示
哪位大哥提供motcpmend.c源文件
555同线电话机互叫铃声电路
ViewMate 8.3 正式版
巧用图像传感器模块参考设计(PRISM) ,简化成像设备从设计到制造的全流程
Rf多功能工具计算软件
我就是我lxw_1602实时时钟
ysjabcd_速度里程计带时间显示.红外调时
电动汽车快速充电教程:分立器件与PIM模块,如何适配不同等级充电桩?
Tcp_Udp测试
uclinux一般使用什么网络播放器?
555无线电呼叫系统编码发射机电路
555遥控电铃电路
TE Connectivity连续12年入选“全球最具商业道德企业”榜单
朔萌阁主_八位灯交叉闪烁
虚拟主机选择指南,让你真正了解互联网!建站空间首选,支持ASP+.NET+PHP+JSP送域名,邮箱,留言版,计数器
PRISM助力成像应用上市时间缩短六个月,实战指南一文解读
瑞萨电子推出28纳米车用微控制器,赋能汽车区域控制
向嵌入式高手请教
四弦_花样流水呼吸灯
存储芯片涨价潮远未结束,深度剖析背后的“超级周期”
555多功能定时呼叫器电路
Rf计算器软件
UCAM使用中铜箔化为Contourize教学
特斯拉招聘半导体晶圆厂建设经理 —— 马斯克雄心勃勃的太拉工厂项目正式启动
解析NVIDIA GTC 2026潜在谋略 黄仁勋如何封锁ASIC对手?
555限时讲话声光报讯器电路
求教ARM芯片的选择
【电源小课堂】巧设电源时序