`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////

`define CLK50M     
//`define CLK24M   // if use fpga_usb ,the system clock is 24m

module top(
    input sys_clk,           //system clock in(for fpga_core is 50mhz;for fpga_usb is 24mhz)
    input sys_rstb,          //system reset,active low
    output [11:0] num_led    //Sboard number led 0-11
    );

`ifdef CLK50M
parameter P_CLK1KHZ = 16'hC350;
`else
parameter P_CLK1KHZ = 16'h5DC0;
`endif    

reg [15:0] count_fre;            //count register for generate 1khz clock        
wire clk1khz;                     //1khz clock for num_led0-3 scaning

always @(posedge sys_clk or negedge sys_rstb)
if(!sys_rstb)
  count_fre <= 0;
else if(count_fre < P_CLK1KHZ)
  count_fre <= count_fre +1;
else
  count_fre <= 0;
 
assign clk1khz = (count_fre == 1);

reg [3:0] number0;           //number led 0 register
reg [3:0] number1;           //number led 1 register
reg [3:0] number2;           //number led 2 register
reg [3:0] number3;           //number led 3 register

reg [7:0] count_1hz;         //count register for generate 1hz clock
always @(posedge sys_clk or negedge sys_rstb)
if(!sys_rstb)
  count_1hz <= 0;
else if(count_1hz < 1000 && clk1khz)
  count_1hz <= count_1hz +1;
else if(clk1khz)
  count_1hz <= 0;

always @(posedge sys_clk or negedge sys_rstb)  // display number0 ++ from 0123
if(!sys_rstb)
  number0 <= 0;
else if(count_1hz == 1 && clk1khz && number0 < 9)
  number0 <= number0 +1;
else if(count_1hz == 1 && clk1khz)
  number0 <= 0;

always @(posedge sys_clk or negedge sys_rstb)  // display number1 ++ from 0123
if(!sys_rstb)
  number1 <= 1;
else if(count_1hz == 1 && clk1khz && number1 < 9 && number0 == 9)
  number1 <= number1 +1;
else if(count_1hz == 1 && clk1khz && number0 == 9)
  number1 <= 0;
 
always @(posedge sys_clk or negedge sys_rstb)  // display number2 ++ from 0123
if(!sys_rstb)
  number2 <= 2;
else if(count_1hz == 1 && clk1khz && number2 < 9 && number1 == 9 && number0 == 9)
  number2 <= number2 +1;
else if(count_1hz == 1 && clk1khz && number1 == 9 && number0 == 9)
  number2 <= 0; 

always @(posedge sys_clk or negedge sys_rstb)  // display number3 ++ from 0123
if(!sys_rstb)
  number3 <= 3;
else if(count_1hz == 1 && clk1khz && number3 < 9 && number2 == 9 && number1 == 9 && number0 == 9)
  number3 <= number3 +1;
else if(count_1hz == 1 && clk1khz  && number2 == 9 && number1 == 9 && number0 == 9)
  number3 <= 0; 
 
 
reg [1:0] state_num;          //choose 0 - 3 number led;
always @(posedge sys_clk or negedge sys_rstb)
if(!sys_rstb)
  state_num <= 0;
else if(clk1khz)
  state_num <= state_num +1;

reg [3:0] tablein;
reg [7:0] tableout;
//0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f,0xf3
always @(tablein)
begin
  case(tablein)
  0:tableout = 8'h3f;
  1:tableout = 8'h06;
  2:tableout = 8'h5b;
  3:tableout = 8'h4f;
  4:tableout = 8'h66;
  5:tableout = 8'h6d;
  6:tableout = 8'h7d;
  7:tableout = 8'h07;
  8:tableout = 8'h7f;
  9:tableout = 8'h6f;
  default:tableout = 8'h3f;
  endcase
end

reg [3:0] num_ch;
reg [7:0] num_d;
reg [2:0] state_mac;
always @(posedge sys_clk or negedge sys_rstb)
if(!sys_rstb)
begin
  num_ch <= 0;
  num_d <= 0;
  tablein <= 0;
  state_mac <= 0;
end
else
  case(state_mac)
  0:begin
      if(clk1khz)
        begin
          num_ch <= 0;
          num_d <= 0;
          state_mac <= 1;
        end
  end
  1:begin
    if(state_num == 0)
      tablein <= number3;
     else if(state_num == 1)
      tablein <= number2;
     else if(state_num == 2)
      tablein <= number1;
     else if(state_num == 3)
      tablein <= number0;
     state_mac <= 2;
  end
  2:begin
    num_d <= tableout;
     state_mac <= 3;
  end
  3:begin
    if(state_num == 0)
      num_ch <= 4'b0001;
     else if(state_num == 1)
      num_ch <= 4'b0010;
     else if(state_num == 2)
      num_ch <= 4'b0100;
     else if(state_num == 3)
      num_ch <= 4'b1000;
     state_mac <= 0;
  end
  default:state_mac <= 0;
  endcase

assign num_led = {num_ch,num_d};

endmodule

专栏文章内容及配图由作者撰写发布，仅供工程师学习之用，如有侵权或者其他违规问题，请联系本站处理。 联系我们