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写verilog程序时提高硬件意识

发布人：0750long 时间：2010-03-12 来源：工程师

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写verilog程序时提高硬件意识

写verilog程序时怎么提高硬件意识？是一个深奥的问题，但是如果你看了下面的程序、电路、仿真，明白什么样的程序生成什么样的电路，绝对能提高你的硬件意识，硬件意识是其中一方面，还要有系统意识。

D-type flip flop

reg q;

always @ (posedge clk)
q <= d;

D type flip flop with asynchronous reset

reg q;

always @ (posedge clk or posedge reset)
if (reset)
q <= 1'b0;
else
q <= d;

D type flip flop with synchronous reset

reg q;

always @ (posedge clk)
if (reset)
q <= 1'b0;
else
q <= d;

D type flip flop with gated clock

reg q;
wire gtd_clk = enable && clk;

always @ (posedge gtd_clk)
q <= d;

Data enbled D type flip flop

reg q;

always @ (posedge clk)
if (enable)
q <= d;

Negative edge triggered D type flip flop

reg q;

always @ (negedge clk)
q <= d;

Latches

Latch

reg q;

always @ (q or enable)
if (enable)
q = d;

Multiplexers

Two input multiplexer (using if else)

reg y;

always @ (a or b or select)
   if (select)
      y = a;
   else
      y = b;

Two input multiplexer (using ternary operator ?:)

wire t = (select ? a : b);

Two input multiplexer (using case statement)

reg w;

// mux version 3
always @ (a or b or select)
   case (select)
      1'b1 : w = a;
      default : w = b;
   endcase

Two input multiplexer (using default assignment and if)

reg p;

// mux version 4
always @ (a or b or select)
   begin
   p = b;
   if (select)
      p = a;
   end

Three input priority encoded mux multiplexer (using if else)

reg q;

always @ (a or b or c or select2)
   if (select2 == 2'b00)
      q = a;
   else
      if (select2 == 2'b01)
         q = b;
      else
         q = c;

Three input priority encoded mux multiplexer (using case)

reg r;

// Priority encoded mux, version 2
always @ (a or b or c or select2)
   begin
   r = c;
   case (select2)
      2'b00: r = a;
      2'b01: r = b;
   endcase
   end

Three input multiplexer with no priority (using case)

reg s;

always @ (a or b or c or select2)
   begin
   case (select2) // synopsys parallel_case
      2'b00: s = a;
      2'b01: s = b;
      default: s = c;
   endcase
   end