//FIFO采用四个always块处理写、读、更新读写指针、FIFO计数

module FIFO (
input [7:0] data_in,
input clk,rst,rd,wr,
output empty,full,
output reg [3:0] fifo_cnt,
output reg [7:0] data_out
);

reg [7:0] fifo_ram[0:7] ;
reg [2:0] wr_prt,rd_prt;

always@ ( posedge clk)
 begin:write
  if(wr&&!full)
   fifo_ram[wr_prt] <= data_in;
  else if( wr&&rd)
   fifo_ram[wr_prt] <= data_in;
 end

always @ (posedge clk)
 begin :read 
  if(rd&&!empty)
   data_out <= fifo_ram[rd_prt];
  else if( rd && wr &&!empty)
   data_out <= fifo_ram[rd_prt];
 end

always @ (posedge clk or negedge reset)
 begin : pointer
  if(!rst)
   begin
    wr_prt <= 0;
    rd_prt <= 0;
   end
  else
   case({rd,wr})
    2'b00:begin
        wr_prt <= wr_prt;
        rd_prt <= rd_prt;
       end
     2'b01:begin
         if(!full)
         wr_prt <= wr_prt+1;
        rd_prt <= rd_prt; 
       end 
     2'b10:begin
         wr_prt <= wr_prt;
         if(!empty)
        rd_prt <= rd_prt+1; 
       end 
     2'b11:begin
         wr_prt <= wr_prt+1;
        rd_prt <= rd_prt+1; 
       end 
    default:begin
         wr_prt <= wr_prt;
         rd_prt <= rd_prt;
         end
   endcase
 end   

always @ ( posedge clk)
 begin:count
  if(!rst)
   fifo_cnt <= 0;
  else begin
   case ({wr,rd})
    2'b00: fifo_cnt <= fifo_cnt;
    2'b01: fifo_cnt <= (fifo_cnt==0)?0:fifo_cnt - 1;
    2'b10: fifo_cnt <= (fifo_cnt==8)?8:fifo_cnt + 1;
    2'b11: fifo_cnt <= fifo_cnt;
    default: fifo_cnt <= fifo_cnt;
   endcase
  end
 end

assign empty = (fifo_cnt == 0);
assign full = (fifo_cnt ==8);

endmodule

endmodule

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