上电清除PUC后, 标准时钟系统UCS的默认状态如下:

· 低频LF模式的XT1被选作XT1CLK的振荡器源. ACLK选择XT1CLK.
· MCLK选择DCOCLKDIV.
· SMCLK选择DCOCLKDIV.
· 锁频环FLL被使能, XT1CLK被作为FLL的参考时钟, FLLREFCLK.
· XIN和XOUT管脚被设置为通用I/0端口功能,所以XT1被禁用,直到这两个I/0端口被设置成XT1模式.
· 如果使用了XT2有效, XT2IN和XT2OUT管脚被设置成通用I/O模式,XT2被禁止.

参考手册中英文手册原文如下:

· XT1 in LF mode is selected as the oscillator source for XT1CLK. XT1CLK is selected for ACLK.
· DCOCLKDIV is selected for MCLK.
· DCOCLKDIV is selected for SMCLK.
· FLL operation is enabled and XT1CLK is selected as the FLL reference clock, FLLREFCLK.
· XIN and XOUT pins are set to general-purpose I/Os and XT1 remains disabled until the I/O ports are
configured for XT1 operation.
· When available, XT2IN and XT2OUT pins are set to general-purpose I/Os and XT2 is disabled.

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