如何使用STATECAD进行多状态机设计实例分析
Next_sreg=M0full;
BP_dcounter = (Std_logic_vector''("00"));
ELSE
Next_sreg=Write0;
BP_dcounter = (( Std_logic_vector''(BP_dcounter1, BP_dcounter0)) +
Std_logic_vector''("01"));
END IF;
WHEN OTHERS =>
END CASE;
END IF;
IF ( RESET=''1'' ) THEN
Next_sreg1=STATE1;
Readcounter = (Std_logic_vector''("00"));
ELSE
CASE Sreg1 IS
WHEN M0empty =>
Next_sreg1=M0readwait;
Readcounter = (( Std_logic_vector''(Readcounter1, Readcounter0)));
WHEN M0readwait =>
IF ( (Sreg=M0full)) THEN
Next_sreg1=Read0;
Readcounter = (( Std_logic_vector''(Readcounter1, Readcounter0)) +
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