library ieee;
      use ieee.std_logic_1164.all;
      entity fifo is
       generic( w: integer :=8;  k: integer :=8 );
       port (clk,reset,wr,rd :in std_logic;
              din :in std_logic_vector( k-1 downto 0);
             dout :out std_logic_vector( k-1 downto 0);
             full,empty :out std_logic);
      end fifo;
      architecture fifo_arch of fifo is
        type memory is array (0 to w-1) of std_logic_vector( k-1 downto 0);
        signal ram:memory;
        signal wp,rp: integer range 0 to w-1;
        signal in_full,in_empty:std_logic;
      begin
      process(clk)
        begin
        if rising_edge(clk) then
           if (wr=''0'' and in_full=''0'') then
               ram(wp)<=din;
           end if;
        end if;
      end process;
      process(clk,reset)
        begin
        if (reset=''1'') then
           wp<=0;
        elsif rising_edge(clk) then
           if (wr=''0'' and in_full=''0'') then
               if(wp=w-1) then
                  wp<=0;
                 else wp<=wp+1;
                end if;
           end if;
         end if;
      end process;
      process(clk,reset)
        begin
        if (reset=''1'') then
           rp<=w-1;
        elsif rising_edge(clk) then
           if (rd=''0'' and in_empty=''0'') then
               if(rp=w-1) then

rp<=0;
                 else rp<=rp+1;
                end if;
           end if;
         end if;
      end process;
      process(clk,reset)
        begin
        if (reset=''1'') then
           in_empty<=''1'';
          elsif rising_edge(clk) then
           if ((rp=wp-2 or (rp=w-1 and wp="1") or (rp=w-2 and wp="0")) and (rd=''0''
      and wr=''1''))then
                 in_empty<=''1'';
             elsif (in_empty=''1'' and wr=''0'') then
                 in_empty<=''0'';
           end if;
         end if;
      end process;
      process(clk,reset)
        begin
         if (reset=''1'') then
            in_full<=''0'';
          elsif  rising_edge(clk) then
            if (rp=wp and wr=''0'' and rd=''1'') then
               in_full<=''1'';
             elsif (in_full=''1'' and rd=''0'') then
               in_full<=''0'';
             end if;
          end if;
      end process;
      full<=in_full;
      empty<=in_empty;
      dout<=ram(rp) when rd=''0'' ;
      end fifo_arch;

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