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# 用Verilog语言实现奇数倍分频电路3分频、5分频、7分频 9

//上升沿触发的分频设计
module three(clkin, clkout);
input clkin;//定义输入端口
output clkout;//定义输出端?

reg [1:0] step1, step;

always @(posedge clkin)
begin
case (step)
2b00: step=2b01;
2b01: step=2b10;
2b10: step=2b00;
default :step=2b00;
endcase
end

always @(negedge clkin)
begin
case (step1)
2b00: step1=2b01;
2b01: step1=2b10;
2b10: step1=2b00;
default :step1=2b00;
endcase
end

assign clkout=~(step[1]|step1[1]);
endmodule

// 如果duty cycle =50%, 可以第一个周期

input clk ;
output throut;
reg q1,q2,d,throut;

always @(posedge clk)
if(!d)
q1=1b1;
else
q1=~q1 ;

always @(negedge clk)
if(!d)
q2=1b1;
else
q2=~q2 ;

always @(q1 or q2)
d=q1q2 ;

always @(posedge d)
throut=~throut;

endmodule

input clkin,rst;
output clkout;
reg [2:0] step1, step2;
always @(posedge clkin )
if(!rst)
step1=3b000;
else
begin
case (step1)
3b000: step1=3b001;
3b001: step1=3b011;
3b011: step1=3b100;
3b100: step1=3b010;
3b010: step1=3b000;
default:step1=3b000;
endcase
end
always @(negedge clkin )
if(!rst)
step2=3b000;
else
begincase (step2)
3b000: step2=3b001;
3b001: step2=3b011;
3b011: step2=3b100;
3b100: step2=3b010;
3b010: step2=3b000;
default:step2=3b000;

endcase
end
assign clkout=step1[0]|step2[0];